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General features
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- Multimaster architecture with integrated RISC processor
- 132 MByte/s transfer rate DMA channel
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Vector generator:
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- 32 bit @ 400 Mhz (2.5 ns edge placement resolution)
- Modular architecture to extend the number of channel
- Sequencer + RAM vector architecture for long and complex sequence generation
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Data bus:
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- 8/16/32 bit programmable
- 400 Mhz update/sample rate(2.5 ns time resolution)
- Address/Data multiplexed
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| I/O optional expansion: |
- Up to 256 I/O
- 128 bit data bus with PMU connection
- Force current/measure voltage, force voltage/measure current on every pin
- Bank programmable I/O voltage
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Address generator:
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- 32 bit @ 200 Mhz
- 4x4 stage pipeline structure for very complex address pattern generation
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Clock generator:
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- Programmable period and duty cycle
- 1.25 ns edge placement resolution
- 400 Mhz max clock frequency
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Event detector and timer:
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- Advance triggering capabilities: edge & level, edge or level, edge before/after level
- 48 bit timer/counter @ 5 ns time resolution with 16 bit programmable prescaler
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1.2 Gbps serial expansion bus
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Up to 32 waveform generators:
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- 12/14 bit resolution @ 100 Msps (10 ns time resolution)
- ±12 V output voltage swing (9 ns rise time) or -9+36 V high voltage option (36 ns rise time)
- 2.5 ns rise time
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PMU current measurement units: |
- 8 parallel channels multiplexed into 128 lines
- 12 bit resolution @ 70 Mhz (14.3 ns time resolution) per channel
- Force current/measure voltage, force voltage/measure current
- Oscilloscope like transient measurements
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| PW0 current measurement unit: |
- 12 bit resolution @ 80 Mhz (12.5 ns time resolution)
- Force current/measure voltage, force voltage/measure current
- Oscilloscope like transient measurements
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